I/O Memory Mapping

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LadderDIP IV has the following memory mapping

 

Note that, when used as I/O pins, the address changes according to the configured direction using two different memory areas.

 

 

Pin Name

Location

(Pinout)

Primary Function

Secondary Function

Address when I/O is configured as INPUT

Address when I/O is configured as OUTPUT

 

 

 

 

 

 

 


IO1

P1-1

I/O

 

%IX0.0

%QX80.0


IO2

P1-2

I/O

 

%IX0.1

%QX80.1


IO3

P1-4

I/O

 

%IX0.2

%QX80.2


IO4

P1-5

I/O

AIN1

%IX0.3

%QX80.3


IO5

P1-6

I/O

AIN2

%IX0.4

%QX80.4


IO6

P1-7

I/O

 

%IX0.5

%QX80.5


IO7

P1-8

I/O

 

%IX0.6

%QX80.6


IO8

P1-9

I/O

 

%IX0.7

%QX80.7


IO9

P1-10

I/O

 

%IX0.8

%QX80.8


IO10

P1-11

I/O

 

%IX0.9

%QX80.9


IO11

P1-12

I/O

 

%IX0.10

%QX80.10


IO12

P1-13

I/O

 

%IX0.11

%QX80.11


IO13

P1-14

I/O

 

%IX0.12

%QX80.12


IO14

P1-15

I/O

AIN3

%IX0.13

%QX80.13


IO15

P2-13

I/O

AIN4

%IX0.14

%QX80.14


IO16

P2-14

I/O

 

%IX0.15

%QX80.15


IO17

P2-16

I/O

 

%IX1.0

%QX81.0


IO18

P2-18

I/O

 

%IX1.1

%QX81.1


IO19

P2-20

I/O

 

%IX1.2

%QX81.2


IO20

P2-21

I/O

 

%IX1.3

%QX81.3


IO21

P2-22

I/O

 

%IX1.4

%QX81.4


IO22

P2-23

I/O

 

%IX1.5

%QX81.5


IO23

P2-24

I/O

 

%IX1.6

%QX81.6


IO24

P2-26

I/O

 

%IX1.7

%QX81.7


IO25

P2-28

I/O

AIN5

%IX1.8

%QX81.8


IO26

P2-30

I/O

AIN6

%IX1.9

%QX81.9


IO27

P2-32

I/O

 

%IX1.10

%QX81.10